Design principles for processor maintainability

With the arrival of large real-time, time-shared systems, the requirement of system reliability has become even more demanding. The result of even a momentary system misbehavior could be catastrophic, since any disruption of service is experienced by all the users on-line at that time. Thus for real-time systems such as telephone switching systems, airline reservation systems, on-line teaching machine, etc., where numerous users are served, and critical real-time systems such as command and control, a high degree of system dependability and maintainability must be realized. Since many of the real-time systems employ the concept of centralization of logic, the overall system reliability objective in large part depends on how well the central processor itself meets the dependability and maintainability objectives. For a processor, the dependability objective often calls for the use of reliable components, conservative circuit design techniques and various redundancy methods. The maintainability objective, on the other hand, demands a processor architecture that is best suited for automatic trouble detection, recovery from faults and fault isolation, so as to insure operational survivability in an environment which is not free of faults. The purpose of this paper is to describe several design principles which may be used in planning processor organization, designing logic circuits, and fault detection and diagnostic tests in order to facilitate the design of a highly maintainable processor for real-time systems. Our scope will be limited to presenting a unified account of some design guidelines, most of which reflect material assembled from a combination of analytical study and practical experience on a realtime time-shared system.! The problem of achieving high dependability by the use of various error detection and correction codes or redundancy techniques has received adequate treatment in the literature,2-4 and will not be included here. In the second section we describe the various observed trouble symptoms and their manifestation in the system. A maintenance sequence for preserving the system's integrity upon occurrence of faults is then suggested. Guidelines for planning a processor organization to achieve high maintainability are diseussed in the third section. Several principles for designing logic circuits and fault detection and diagnostic tests are described in the fourth section.